The present invention relates to digital signal processing, and, more particularly, to a frequency locked loop and a frequency difference detector as implemented, for example, in a digital data regenerator.
Digital signals are widely used in telecommunications in the transmission of, for example, multiplexed pulse code modulated (PCM) voice channels over twisted pair, coaxial cable or optical media. These digital transmission rely on regularly spaced regenerators to reconstruct the data stream by cancelling the effects of loss, dispersion and noise in the transmission medium before these effects become irreversibly large. The operation of regenerators can be generalized from the following description pertaining to simple binary data, e.g., unipolar no-return-to-zero (NRZ) data.
A digital binary signal originates as a bi-level step function with sharply defined transitions and a consistent bit rate. This well-defined form is eroded by loss, dispersion and noise during transmission. Upon reception, the degraded signal can be amplified and limited or can be applied to a comparator, or other decision-making circuit, to yield again a two-level signal with sharp transitions. However, the restored transitions do not generally match the original transition times. The new transitions tend to "jitter", i.e., vary randomly about the nominal transition time.
Basic regeneration strategies to sample the resharpened signal on a clock transition coinciding with the midpoint of a bit period so as to minimize the effects of this jitter. The challenge is to determine the proper clock signal from the data stream itself.
While the frequency spectrum of the bit stream has a null at the baud frequency, reliable timing information exists in the data transitions. This timing can be extracted by differentiating the re-sharpened signal to yield a train of pulses of alternating polarity, which can be rectified to provide a timing signal in the form of a train of uniform-polarity pulses identifying data transitions.
If the incoming data were in the form of alternating zeroes and ones, this timing signal would have a pulse rate equal to the baud rate of the incoming data. More often, the timing signal takes the form of a pulse train with such a pulse rate, but with randomly selected pulses missing.
For example, random data reproduces a transition pulse waveform that looks like a pulse train at the baud frequency with missing pulses. Such a pulse stream has a verty strong spectral component at the baud frequency. With the proper filtering, amplification, and phase shifting the baud frequency component in the transition pulse spectrum can be processed into the clock signal required to regenerate the incoming data.
A phase locked loop can lock onto a very small spectral component in a pulse train so that long strips of ones or zeroes have negligible effect on timing phase or amplitude. Thus, a phase locked loop can be used to fill in the missing pulses in a pulse train and eliminate jitter.
Conventional phase locked loops require a design trade-off between stability and capture range. This limitation has been partially overcome by the substitution of frequency/phase locked loops. These devices use a frequency locked loop during an acquisition mode when capture range is the primary concern. Once the proper frequency is locked, the loop is dominated by a parallel phase locked loop, which provides stability during steady-state mode operation.
Such frequency/phase locked loops are disclosed in U.S. Pat. No. 4,015,083 to Bellisio and in R. R. Cordell et al., "A 50 MHz Phase- and Frequency-Locked Loop", IEEE Journal of Solid-State Circuits, VOL. SC-14, No. 6, December 1979, pp. 1003-1009. In these disclosures a phase locked loop and a frequency locked loop share a loop filter, a controlled oscillator and a phase shifter. The phase locked loop is conventional and includes a multiplier and a low pass filter. The frequency locked loop includes a frequency difference detector, and a filter.
The outputs of the respective filters are summed and conveyed to the shared loop filter. The gains of the two loops are such that the frequency locked loop dominates the controlled oscillator during acquisition until frequency lock is achieved. Once frequency lock is achieved, the phase locked loop dominates to attain and maintain phase lock.
Referring to the Bellisio patent, the frequency difference detector includes parallel in-phase and quadrature branches. The in-phase branch includes a multiplier at which an extracted timing signal is multiplied by an in-phase version of the oscillator output. A low pass filter rejects the upper sideband to yield a signal at the difference, i.e., "beat", frequency of the multiplier inputs. A comparator converts the beat signal into a square wave at the beat frequency. A differentiator then converts this square wave into a train of alternating polarity pulses having a pulse rate twice the beat frequency.
The quadrature branch of the frequency difference detector also includes a multiplier, a low pass filter and a comparator. The inputs to this multiplier are the extracted timing signal and a phase-shifted version of the oscillator output. The multiplier, the low pass filter, and the comparator of the quadrature branch perform the same functions as their counterparts in the in-phase branch, in this case yielding a square wave at the same beat frequency, but 90.degree. out-of-phase with respect to the square wave in the in-phase branch. The quadrature branch also includes a capacitor or other means for eliminating any non-zero DC component of the quadrature square wave.
The alternating polarity pulse train output from the in-phase branch is multiplied by the ac-coupled quadrature square wave from the square-wave branch to yield a consistent polarity pulse train. The pulse rate of this train is twice the difference frequency of the timing signal and oscillator output; the sign of the polarity represents the sign of the frequency difference. For example, if the timing frequency exceeds the oscillator frequency, the output of the frequency detector has a positive polarity, and the polarity is negative under the opposite circumstances.
While rapid and wide-range acquisition and good stability can be achieved for a given nominal baud rate, the disclosed system does not provide optimally for self-timed regeneration of signals with widely differing baud rates. A reason for the limited baud rate of frequency locked loops is that the components required to provide a proper balance of acquisition range and speed on the one hand, and stability on the other hand are baud-rate dependent.
A very limited solution to this problem has been to arrange a regeneration system so that the necessary components of the frequency difference detector can be readily replaced. For example, the low pass filters and a pulse-width determining capacitor of the differentiator of the frequency difference detector can be arranged for ready replacement when the frequency locked loop is used at different baud rates.
Whereas most of a regeneration system can be and should be implemented on a single chip to provide enhanced performance and reliability at lower cost, the components needing replacement are typically left off-chip. While the off-chip components may include only a few capacitors and such per regenerator, the off-chip components amount to a multiplier of parts count for large multi-regenerator systems. Also, manufacturing costs increase and reliability goes down with the increased parts count. For many applications, especially satellite communications, bulk and power consumption are adversely affected by discrete components.
What is needed is a frequency locked loop with both rapid and wide-range acquisition and optimal stability which can be used for a broad range of nominal baud rates. In particular, a frequency difference detector for such a frequency locked loop is needed which minimizes the component replacement required to optimize performance at different baud rates.